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...Register file size limits gpu scalability fle rf already accounts for of on chip storage but there is still demand more registers to maximum required x achieve performance and concurrency average available kb future slow memory accesses call threads multi socket rdma nvm etc need mechanisms expand compiler optimizations per capacity without large area power thread overheads loop unrolling coarsening how make files larger emerging technologies compression virtualization c p i d e z l common challenge latency overhead a no m r o example with ntv tfet n slower ideal real lavamd lbm leukocyte myocyte nn sad sgemm sto wp gmean goal tolerate latencies contributions tolerant ltrf level main cache performs prefetch ops while executing other warps paves the way several driven prefetching break control flow graph into tolerates up subgraphs at beginning each use case subgraph larintegerrv arl fan al ysis id ehintigherfy pre fperetch fosubrmagrapnhcse outline background challenges in gpus archite...