The words contained in this file might help you see if this file matches what you are looking for:

...Outline gate sizing in vlsi design previous work challenges high performance with a signoff timer overall flow experimental results conclusions and future effective approach to power delay optimization objective minimize satisfy constraints slack slew max load capacitance tunable cell parameters width vth length select proper library for each invx drive strength multi hvt nvt lvt l bias lgate nm lower leakage higher speed techniques common heuristics algorithms convex continuous linear programming lagrangian relaxation discrete dynamic sensitivity based limitations industrial libraries have sizes rounding solutions may be suboptimal np hard problem scalability issue do not account realistic models capaci tance our extends trident produced strongest on ispd benchmarks as of iccad metaheuristic importance sampling guided search limitation no interconnect calculation unrealistic assumption inaccurate internal critical paths...