File: 7176ii 3rd Semester Computer Science And Engineering
DIGITAL LOGIC DESIGN RD 3 sem CSE Faculty Name: MITALI PANDA Content Module-II: Minimization of Boolean Functions: Karnaugh Map, Don’t care conditions, Prime Implicants, Quine- McCluskey technique, Logic gates ...
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...Digital logic design rd sem cse faculty name mitali panda content module ii minimization of boolean functions karnaugh map don t care conditions prime implicants quine mccluskey technique gates nand nor universal maps k a method for graphically determining and implicates function was developed by veitch modified the involves diagrammatic representation algebra this graphic is called it seen that truth table can be used to represent complete n variables since each variable have value or has rows consist two parts an tuple which corresponds assignment functional geometrical configuration cells such tuples row uniquely locates cell on values assigned are placed as entries in i e associated significant about construction arrangement physically adjacent within if only their respective differ exactly one element so law x cab applied ex these vary needs number four following figure shows there possibility grouping min terms possible combinations m eight three then becomes sixteen let r repres...